The present invention relates to a memory organization and more particularly to an organization of memory elements or arrays, each array having both a standard data port and an alternate data port, to increase design flexibility. The standard port is available in the event the array is intended for high-end applications where speed is of paramount importance, and the alternate port is available in the event the array is intended for low-end applications where cost is of paramount importance. The memory array design of the present invention utilizes a special buffer associated with each array to permit the address port of each memory array element or chip to function as an alternate data port for the array, thereby reducing the number of external input/output (I/O) circuits required for communication with each array. The standard data port is not affected.
In most typical data processing applications, the memory unit communicates with a separate data processing unit through various buses or lines, such as the prior art block diagram arrangement of FIG. 1. In this simplified illustration, memory system 10 communicates with separate processor 11 through an address bus and a data bus. Each bus typically contains a number of lines equal to the number of bits in each address word or data word. Various control and power lines (not shown) may also be present.
Conventional random access memory (RAM) designs employ one or more memory chips or arrays of cells. Each array typically will have an address port through which the address lines from the processor pass, and a separate data port through which the data lines pass. Separate ports are normally required because of the need to decode address words but not data words, and the possibility of interference if address and data words are both transmitted through the same port.
Dual port and multiple port memories are known. See, e.g., U.S. Pat. Nos. 4,541,076; 4,410,964; 4,633,440; 4,491,937; and 4,718,039. The memory designs of these patents permit data to be read into or out of the memory array through more than one port. However, separate address ports must still be provided for the address information. In addition, merely increasing the number of ports through which information may pass creates certain problems. For example, for each additional port, additional I/O circuitry typically must also be provided both in the array and in the processor or external support logic circuitry to act as interface devices to facilitate the transfer of data or address information back and forth through the additional port. Each additional I/O circuit, of course, adds to the complexity and cost of the memory and support circuitry, and also requires more power, generates more heat, takes up more chip space and reduces reliability.
Aside from the problems caused by additional I/O circuits, there are other design and manufacturing considerations that also arise when considering the number of address and/or data ports to provide for each array. Because of the increasing complexity with each new generation of memory chip, it is desirable to have as few different designs as possible to minimize design costs. A standard or uniform chip usable for a wide variety of applications, both high-end and low-end, would be highly desirable. If the same memory chip could be used in both a low-cost, relatively-low speed data processing product and in a higher cost but higher speed product, great savings and design flexibility could be achieved.
In order for a given memory chip to be as versatile as possible, it will, of course, need to be designed to handle the highest speed envisioned for its particular range of applications. Thus, the I/O circuitry and data port should be designed to handle high-speed data transfer to and from the array of memory cells, and the address port should be designed to handle high-speed addressing of the greatest number of cells expected to be needed for the range of applications. For large arrays, this usually means that more address lines than data lines should be provided, thus requiring at least two separate ports, one for address and one for data.
Although such a design is suitable for high-speed applications, where a large number of I/O circuits may be an acceptable trade-off to achieve speed, it is less suitable for low-cost applications where the cost of additional I/O circuits to support separate or additional ports would not be justified. Because of this, it is desirable to have a memory circuit or chip with the capability of being easily adapted for either high-speed or low-cost applications. In particular, it would be desirable to be able to use the same memory chip for either a two-port application or a single-port application. For example, if one port could be used for both data and address information, conventional address I/O circuits could also handle the data, eliminating the need for additional I/O circuits dedicated to the data port for low-cost applications. The combined address/data port should not, however, interfere with the data port or otherwise adversely affect chip performance, to permit the dedicated data port to be used for high-speed applications. The present invention accomplishes these objectives through the use of a special on-chip data buffer that permits the address port to operate both as an address port and as an alternate data port.
In U.S. Pat. No. 4,694,394, there is disclosed a microprocessor system having a multiplexed address/data bus. This patent shows a combined address/data bus entering what appears to be an address/data port in "circuit block 2". This element is further identified in the specification as being a commercial integrated circuit containing a RAM manufactured by Intel Corp., identified by the code "8155." Little additional structure or function, however, is disclosed either in the patent or in the available literature for this Intel product. For example, the Intel 1988 Embedded Controller Handbook, pp. 16-31 to 16-37 (copyright 1987), describes the product as having a static RAM array, several I/O ports, a multiplexed address and data bus, a timer and an address latch. It does not appear, however, that this product contains two different data ports suitable for use in both high-end and low-end applications. In addition, there is no disclosure of a data buffer.
U.S. Pat. No. 4,443,864 discloses a memory system having a multiplexed address/data bus. The bus of this patent, however, requires a certain number of dedicated address lines. In addition, there is no disclosure of a separate data port permitting the memory array to function in widely varying application.
In U.S. Pat. No. 4,491,937, a multiple port storage array is disclosed, having multiple write ports and multiple read ports. The row address lines or column address lines may also be used to carry data. U.S. Pat. No. 4,443,845 discloses a memory system having a "common interface." The device of this patent shows a memory connected to a processor with a "common bus" which carries address, data and control signals. The above two patents do not, however, disclose data buffers or alternate data ports permitting the memory to operate in both high-end and low-end applications. The present invention is intended to remedy the above-mentioned omissions and disadvantages of the prior art and provide a memory capable of being adapted for use in a wide variety of applications. More particularly, the present invention relates to a memory chip having both a standard data port, suitable for normal or high-speed use, and a separate address port which may double as an alternate data port, suitable for use in low-cost, lower speed applications where the number of external I/O circuits is to be kept to a minimum. When the alternate data port is used, more performance may be obtained from existing address line I/O circuits. Data is kept from interfering with the address signals and vice versa by way of a special data buffer located on the memory chip, operating with timing signals. The data buffer serves to latch, gate and drive the data signals to and from the memory array through the address port. A type of "triplexing" is achieved on the address lines in that column address, row address and data signals are all transmitted over the same lines and through the address port in proper timed relationship with each other so as to avoid mutual interference. This permits the memory chip to function either as a single-port chip or as a dual-port chip.